The present invention relates generally to semiconductor device manufacturing techniques and, more particularly, to a copper interconnect structure with an amorphous tantalum iridium diffusion barrier.
As integrated circuit device size continues to shrink in order to achieve higher operating frequencies, lower power consumption, and overall higher productivity, the copper interconnections formed by the so-called dual damascene process have faced increasing difficulties with respect to both manufacturing and performance. In particular, since the interconnect feature sizes (e.g., the width of the copper lines and the diameter of the via holes) are getting smaller, filling of the etched trench/via structures with copper by electroplating becomes more difficult. Electroplating of copper takes place on a copper seed layer that, in turn, is formed on top of a liner material by physical vapor deposition (PVD).
However, because of the limited conformity of the copper seed layer, the seed layer may have one or more discontinuities therein. At such locations where the copper seed is discontinuous, the surface of the liner therebeneath (which is usually tantalum (Ta) or tantalum nitride (TaN)) working as a copper diffusion barrier becomes exposed to the air after the PVD process and gets oxidized. Consequently, the electroplating of copper does not take place on top of the oxidized liner surface because the electron supply for copper ions (which is a necessary reaction for the electroplating of copper) is inhibited at the oxidized liner surface. As a result, the discontinuous portion of the seed layer has an interface with copper wherein the atomic bonding is so weak that the discontinuity works as a void nucleation site during the annealing process. The annealing process in turn is used to grow the copper grains large for reliability enhancement of the interconnect system. Subsequently, the void nucleation site causes void formation either during the annealing process or the subsequent heating processes to form further metal layers to complete the chip manufacturing. It is also possible that void nucleations may adversely affect chip operation due to electromigration or other stress-induced migration phenomena. In summary, such void nucleations result in either low production yield or low product reliability.